Computer Organization

The course “Computer Organization” deals with the operation of the basic units that form a computer system. It presents the basic design parameters of a processor, such as the organization, the instruction set, the CPU, and the cache and virtual memories. It describes the development of software routines in symbolic language and their execution on a RISC processor (MIPS). In addition, it analyzes the pipeline technique, the methods to cope with the introduced hazards and its application to a processor design. Finally, it describes the operation of cache and virtual memory and the techniques to enhance their performance.

Objectives

The in-depth understanding of the issues of: Organization (Architecture) of RISC processors. Instuction set of a RISC processor (MIPS) Software execution: Translation of high-level language into symbolic language. Execution of symbolic-language instructions. Algorithms for executing arithmetic operations (addition, subtraction, multiplication, division) in floating-point and fixed-point arithmetic. Design of MIPS CPU: Design (sub-systems and interconnection) of one-cycle CPU, Design of pipelined CPU, Hazards (structural, data, control) in pipelined designs Cache and Virtual memory operation, Design techniques and methods for performance enhancement of cache and virtual memory

Prerequisites

Basic knowledge of programming and Digital Logic Design

Syllabus

General Terms: Computer History, Program execution, Performance and energy consumption, One-core & Multi-core systems. Computer’s language: Hardware operations, MIPS instruction set (arithmetic and logic instructions, branching instructions), Procedures and Functions, Instruction addressing, Program compilation and execution. Computer arithmetic: Algorithms for addition, subtraction, multiplication, and division, Floating-point arithmetic. Processor: CPU design (data-path and control circuits), Pipeline, Performance of computer systems, Design of pipelined processor. Memory: Types of memory circuits, Memory hierarchy, Cache memory, Performance of cache memory, Virtual memory.