Digital Logic Design

The target of the course “Digital Logic Design” is the in-depth understanding of the theory for designing synchronous and asynchronous sequential digital circuits. It deals with the methodologies of analysis and design of registers and counters along with the design at Register Transfer Level (RTL). In addition, it studies the basic memory structures (RAM, ROM) and programmable logic structures (PAL, PLA, PLD, FPGA). Upon the completion of the course, the student will have understood in details the theory and the main issues for designing sequential circuits and will be able to apply techniques and methods to: a) analyze the operation and b) design (states reduction and assignment) synchronous sequential circuits. Moreover, they will be able to: a) analyze the operation of asynchronous sequential circuits and b) to apply methods and techniques for designing asynchronous sequential circuits avoiding races and hazards.

Objectives

The goals of the course are: The in-depth understanding of the theory for designing synchronous and a synchronous sequential digital circuits The analysis and design of synchronous sequential digital circuits The analysis and design of registers and counters The study of basic memory structures (RAM, ROM) and programmable logic structures (PAL, PLA, PLD, FPGA) The design at Register Transfer Level (RTL Design) The analysis and design of asynchronous sequential digital circuits

Prerequisites

Basic knowledge on digital design, Logic design of combinational circuits

Syllabus

Synchronous Sequential Logic: Introduction, Basic sequential circuits (latches and flip-flops), Analysis of Clocked Sequential Circuits (state equations, state tables, and state diagrams), State reduction and assignment, Finite state machines (Moore & Mealy machines), Design Procedure (design using JK, D, and T flip-flops), Design examples. Registers and counters: Shift registers (parallel/serial load, bidirectional shift registers etc.), Ripple counters (binary, BCD counters), Synchronous counters, Ring and Johnson counters. Memory and Programmable Logic: Introduction, Random-Access Memory, (read, write, timing, types of RAMs), Memory decoding, Error detection and correction, Read-Only Memory, Programmable Logic (PLAs, PALs, PLDs, FPGAs). Register Transfer Level (RTL) Design: Introduction and terminology, Algorithmic state machines – ASMs, (ASM diagrams, reduction and optimization), Control logic, Design with multiplexers, Design avoiding races, Design examples. Asynchronous Sequential Logic: Introduction, Analysis procedure, Circuits with latches. Design procedure, Reduction of state and flow tables, Race-free state assignment, Hazards. Design examples.